DSP ASIC module Design for natural frequency of ECG signal

This study implemented software to hardware design for a part of ECG system which is intended to detect and classify atrial fibrillation. The feature extraction process was chosen to be implemented into hardware design. The chosen algorithm was the natural frequency of ECG signal that was obtained from second-order system. Steps taken from digital signal processing to signal processing in hardware on Field-programmable gated-array (FPGA) is discussed. By optimizing resource utilization, the performance was analyzed for 2 hardware designs, Design 1 and Design 2 that needed 34 and 29 resource utilizations, respectively. Results from QuartusII shows Design 2 used less logic utilization than Design 1, i.e. 36 as compared to 2530. Therefore, Design 2 is considered a better design.