A sequential circuit fault tolerance technique with enhanced area and power

Increasing rates of soft errors at the nanometer scale require effective fault tolerant solutions. Recently, a finite state machine (FSM) based fault tolerance technique for sequential circuits has been proposed. The technique is based on protecting few states with high probability of occurrence by adding equivalent redundant states. The resulting state assignment solution satisfies the fault tolerance requirements but has no control on the area or power of synthesized sequential circuits. In this work, we propose an algorithm that starts with a given state assignment solution targeting the optimization of power and generates a state assignment solution that preserves the original assignment and satisfies the fault tolerance requirements. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesized sequential circuits while enhancing their fault tolerance.