A 0.13?m CMOS 5-MHz BW 47-dB SNDR all-digital time-mode first-order as ADC with 3-bit gated VCO quantizer

This paper presents an all-digital time-mode first-order ΔΣ ADC with 3-bit gated VCO quantizer. The ΔΣ ADC consists of a voltage-to-time integrator that performs both voltage-to-time conversion and feedback subtraction, a 7-stage gated current-starved ring oscillator as a 3-bit quantizer, and a digital differentiator that provides both first-order noise-shaping and frequency feedback. Implemented in IBM 0.13 μm 1.2V CMOS technology, the ADC provides SNDR of 47.4 dB and SFDR of 34.1 dB over 4 MHz bandwidth. The power consumption of the ADC is 1.1mW. The silicon consumption excluding bonding pads of the ADC is 470 × 470 μm2.