An attempt to improve output voltage quality of developed multi-level inverter topology by increasing the number of levels

In this paper, an improved Cascaded Multi-Level Inverter (CMLI) topology which can be "symmetric" or "asymmetric" is proposed. The improved topology can produce higher number of levels using lower number of components. Higher number of levels leads to generation of a high quality with low Total Harmonic Distortion (THD) output voltage waveform. To increase number of voltage levels, two algorithms are proposed for determination of magnitude of dc voltage sources, which are investigated and the most effective one is introduced. To verify operation of proposed topology, it is modeled and simulated in PSCAD/EMTDC software. Proper performance of proposed topology is confirmed by obtained simulation results.