FPGA implementation of comb-based decimation filter with improved frequency characteristic for SD A/D converters application

This paper describes a FPGA implementation of a low-complexity comb-based decimation filter with improved frequency characteristics in both, the passband and the folding bands. The attenuation across the folding bands is increased by two cosine filters in cascade, while the simple compensator, which work at low rate, decrease the resulting filter passband droop. The overall structure is multiplierless and was fitted into the Spartan 3A (3s700afg484-4) FPGA device from Xilinx, to prove a low resource implementation.