A 10 Gbps ADC-based equalizer for serial I/O receiver

This paper introduces the system architecture and implementation of a 10Gbps ADC-Based Equalizer for Serial I/O Receiver. The system consists of 2 main building blocks. The first is a 4-channel 4-bit flash analog-to-digital converter with 10 Gbps sampling speed which was implemented using a modified clocking scheme that improves the ADC accuracy and resolution without the need for digital calibration. The ADC achieves a figure of merit of 115 fJ/conversion-step, and was tested for input signals up to 5GHz. The second block is a 2-tap FFE, 3-tap DFE, 10-Gbps digital adaptive equalizer. The equalizer is capable of compensating more than 40 dB of attenuation at Nyquist frequency. The adaptive algorithm used is LMS algorithm using either training sequence mode or blind equalization mode. The system was designed using 65nm CMOS technology.