DocumentCode :
3740651
Title :
Trigeneous Platforms for Energy Efficient Computing of HPC Applications
Author :
Santhosh Kumar Rethinagiri;Oscar Palomar;Javier Arias Moreno;Osman Unsal;Adrian Cristal
Author_Institution :
BSC-Microsoft Res. Center, Spain
fYear :
2015
Firstpage :
264
Lastpage :
274
Abstract :
In this paper, we present two novel real-time heterogeneous platforms with three kinds of devices (CPU, GPU, FPGA), i.e. trigeneous platforms, for efficiently accelerating computation intensive applications in both the high-performance computing and the embedded system domains. In the high-performance computing domain, the entire platform is implemented on a workstation which consists of an Intel Xeon E5 processor, a Nvidia Tesla GPU and a Xilinx Virtex 7 FPGA. The second platform is built for achieving high-performance in the real-time embedded system domain. For this platform, we use a Xilinx Zynq and Nvidia Jetson TK1 board. In these platforms, the communication is performed using PCIe Gen3 and PCIe Gen2 cards respectively. We conducted experiments using 5 real-time and high throughput computation-data-intensive applications, namely cone beam computed tomography, face recognition, HEVC UHD decoding, number plate recognition and motion tracking. All the applications are mapped to the devices of the proposed trigeneous platforms, based on the energy efficiency of the different tasks on each device but also minimizing data transfers and maximizing parallelism. With this trigeneous platform, we are able to achieve an average speed-up of 21x compared to a CPU-GPU platform, 24x compared to a CPU-FPGA platform and 70x compared to Quad-core CPU alone execution. The proposed trigeneous platforms save 43%, 56% and 64% of the energy when compared to CPU-GPU, CPU-FPGA and quad-core CPU platforms respectively. Furthermore, we also implemented these applications by using a single programming language (OpenCL) on the trigeneous platforms and achieved 6x of speed-up on average over the quad-core setup.
Keywords :
"Field programmable gate arrays","Graphics processing units","Real-time systems","Prototypes","Computer architecture","Performance evaluation","Acceleration"
Publisher :
ieee
Conference_Titel :
High Performance Computing (HiPC), 2015 IEEE 22nd International Conference on
Type :
conf
DOI :
10.1109/HiPC.2015.19
Filename :
7397641
Link To Document :
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