Title :
FPGA implementation of authenticated encryption algorithm Minalpher
Author :
Makiko Kosug;Masahiro Yasuda;Akashi Satoh
Author_Institution :
Department of Communication Engineering and Informatics, The University of Electro-Communications, Chofu, Tokyo, Japan
Abstract :
A new authenticated encryption algorithm Minalpher [1] submitted to CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) [2] was implemented on various FPGA devices with straightforward and pipelined hardware architectures. Then, its performances in operating speed, hardware size, and power consumption were compared with a current standard algorithm AES-GCM [3] to show the advantages of Minalpher in compact and high-speed hardware implementations.
Keywords :
"Computer architecture","Hardware","Throughput","Field programmable gate arrays","Encryption","Power demand","Microprocessors"
Conference_Titel :
Consumer Electronics (GCCE), 2015 IEEE 4th Global Conference on
DOI :
10.1109/GCCE.2015.7398679