An efficient network on chip design flow

As technology scales and VLSI systems become more and more complex, both bus and crossbar-based architectures are no longer suitable for implementing communications between the system components. Thus, a specific NoC is needed so as to meet the user-defined constraints (area, bandwidth, energy dissipation) while ensuring system reliability. The NoC design flow which is presented in [1] addresses related research problems and includes solutions to cope with them. In this paper, we present a quite different NoC design flow that targets the following features: i) the NoC is customized and distributed; ii) the generated NoC architecture is dedicated to design either real-time systems or high-throughput ones while meeting the area and power dissipation constraints; iii) the system reliability problem is addressed.