Design and implementation of a configurable NoC

This paper presents a configurable and low latency NoC. The RTL architecture is designed and implemented on an FPGA platform. In order to reduce the latency, we apply the look-ahead XY routing algorithm and improve the framework of the traditional virtual channel allocator, as well as the switch channel allocator. The synthesis report shows that the proposed router reaches a good balance between timing closure and resource consumption. The simulation results of network latency and throughput show that the NoC design provides excellent communication performance.