Shared CSD complex constant multiplier for parallel FFT processors

This paper presents a shared canonical signed digit (CSD) complex constant multiplier for high-speed low-complexity parallel fast Fourier transform (FFT) processors. To reduce the number of twiddle factor (TF) multiplications, the mixed radix -24/23 FFT algorithm is adopted for FFT processor. The 512-point FFT processor using the proposed shared CSD complex constant multiplier has been designed and implemented using 90-nm CMOS technology. Synthesis results show that the proposed FFT processor achieve a higher throughput rate up to 3.2 GS/s at 400 MHz while requiring much less hardware complexity with respect to other FFT processors. The SQNR performance is 36dB with 12-bit word-length implementation.