Static leakage control in null convention logic standard cells in 28 nm UTBB-FDSOI CMOS

A key advantage of asynchronous systems, in which the clock is re-placed by local handshaking signals between functional units, is their ability to operate correctly across a wide range of conditions including supply, temperature, aging and manufacturing variability. In this letter, we describe the design, simulation and layout of a representative example of a quasi-delay-insensitive asynchronous logic family, Null Convention Logic, based on a 28nm ultra-thin body and box, fully depleted silicon-on-insulator (UTBB-FDSOI) process. This technology choice supports a flexible trade-off between leakage power and performance using substrate/well bias, including a potential for temperature dependent biasing. Simulation results indicate that it is possible to reduce the effects of increased temperature on leakage current by more than 2X with a small impact (~10%) on propagation delay.