Title :
Model-based CMP (Chemical-Mechanical Polishing) proximity correction for mitigating systematic process variations
Author :
Yongchan Ban;Yongseok Kang;Woohyun Paik
Author_Institution :
System IC R&D Lab., LG Electronics 19, Yangjae-daero 11gil, Seocho-gu, Seoul 137-130, South Korea
Abstract :
In this paper we have proposed a way of a model-based CMP proximity correction in sub-28nm SoC (system-on-a-chip) designs. Just like OPC (optical proximity correction) process against lithography variations, the proposed approach can be added at the mask synthesis stage in addition to the conventional metal fill approach and highly reduces the systematic process variation due to CMP.
Keywords :
"Layout","Copper","Integrated circuit interconnections","Lithography","Resistance","Systematics"
Conference_Titel :
SoC Design Conference (ISOCC), 2015 International
DOI :
10.1109/ISOCC.2015.7401685
