Managing clock skews in clock trees with local clock skew requirements using adjustable delay buffers

The problem of meeting the skew constraint in clock trees becomes much hard as the IC design paradigm has been shifting to multiple power supply mode design, in which the clock skew varies dynamically according to the voltage levels of the applied power modes during the execution. As a remedy to deal with the clock skew optimization problem of the designs with multiple power modes, which are now a mainstream for low power designs, many researches have focused on the utilization of adjustable delay buffers (ADBs), whose delay can be adjusted dynamically, and attempted to replace the fewest number of clock tree buffers with ADBs. However, none of the works have considered the local clock skew requirements in clock trees, and the clock trees are optimized pessimistically, resulting in excess ADB insertion. In this work, we propose a solution to the problem of ADB insertion to resolve the difference of local clock skews in clock trees. Through experiments with benchmark circuits, it is shown that our proposed solution is able to reduce the number of ADBs by 21% on average over that of the conventional local skew-unaware ADB insertion method for clock trees with multiple power modes.