A CMOS image sensor with non-memory capacitor two-step single slope ADC for high frame rate

This paper proposes a column-parallel two-step Single-Slope Analog-to-Digital Converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a very simple digital column circuit consisting of a coarse counter (coarse step counter) and a 4-to-16 decoder. The second ramp (fine ramp) slope has only one slope generator, regardless of the results of the first ramp decisions, to eliminate the slope mismatch between fine ramp slopes. The maximum frame rate of the proposed VGA CMOS Image Sensor (CIS) is 320 frames per second (fps). The total power consumption is 72 mW from supply voltages of 2.8 V(analog) and 1.5 V (digital). The Figure of Merit (FoM) is 2.01 [e-nJ].