• DocumentCode
    3742686
  • Title

    Efficient scheduling scheme for eight-parallel MDC FFT processor

  • Author

    Jeong Keun Jang;Moon Gi Kim;Myung Hoon Sunwoo

  • Author_Institution
    School of Electrical and Computer Engineering Ajou University, San 5, Woncheon-Dong, Yeongtong-Gu, Suwon, 443-749, Korea
  • fYear
    2015
  • Firstpage
    277
  • Lastpage
    278
  • Abstract
    This paper presents a new eight-parallel multi-path delay commutator (MDC) FFT processor based on the novel modified radix-26 FFT algorithm. The proposed FFT processor can achieve a high throughput and a low hardware complexity by using the efficient scheduling scheme that reorders data-paths. The proposed scheduling scheme and CSD approach can reduce the number of complex multipliers.
  • Keywords
    "Throughput","Processor scheduling","Algorithm design and analysis","OFDM","Hardware","Signal processing algorithms","Complexity theory"
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2015 International
  • Type

    conf

  • DOI
    10.1109/ISOCC.2015.7401755
  • Filename
    7401755
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3742686