Low-power cache memory with state-of-the-art STT-MRAM for high-performance processors

This paper describes state-of-the-art STT-MRAM, which can drastically save energy consumption dissipated in cache memory system compared with conventional SRAM-based ones. This paper also presents how to build cache memory hierarchy with both the state-of-art STT-MRAM and SRAM to reduce cache energy consumption. The key point is "break-even-time aware memory design" based on normally-off operation. For further power reduction, an intelligent power management technique for the STT-MRAM-based cache is also discussed.