DocumentCode
3742710
Title
Hardware implementation of HEVC CABAC encoder
Author
Doohwan Kim;Jeonhak Moon;Seongsoo Lee
Author_Institution
School of Electronic Engineering, Soongsil University, Seoul, Korea
fYear
2015
Firstpage
183
Lastpage
184
Abstract
CABAC is high-compression-ratio entropy coding in HEVC, but it is difficult to be parallelized for speedup. In this paper, a pipelined HEVC CABAC architecture is proposed to increase operating frequency. The proposed CABAC encoder was implemented in 0.18um technology with 158 MHz operating frequency and 45,088 gate counts.
Keywords
"Context","Context modeling","Bismuth","Logic gates","Solid modeling","Syntactics","Engines"
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2015 International
Type
conf
DOI
10.1109/ISOCC.2015.7401779
Filename
7401779
Link To Document