DocumentCode
3742725
Title
The hardware accelerator of the automatic speech recognition for the continuous Korean words
Author
Juyeob Kim;Yunjoo Kim;Wonjong Kim;Joohyun Lee
Author_Institution
SW-SoC Convergence Research Division, Electronics and Telecommunications Research Institute, Gajeong-ro, Yuseong-gu, Daejeon, 305-700, South Korea
fYear
2015
Firstpage
213
Lastpage
214
Abstract
This paper describes the hardware of the speech recognition. The embedded speech recognizer should meet two conditions for the low-latency performance and the low-power dissipation. So, we made the fully-hardwired speech recognizer as the hardware accelerator to offload the system processor without the support of the remote computing environment. Our overall design was designed and implemented on FPGA board. Our design showed speedy response as the real time factor of 0.4 ~ 0.5 at 100MHz operating frequency and uses the HW resource of 10.
Keywords
"Hidden Markov models","Mel frequency cepstral coefficient","Discrete cosine transforms","Field programmable gate arrays"
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2015 International
Type
conf
DOI
10.1109/ISOCC.2015.7401794
Filename
7401794
Link To Document