FPGA hardware architecture with parallel data processing to detect moving objects using the background image subtraction technique

Moving objects can be recognized through detection systems that use computer vision as it passes in front of a digital camera. However, a major challenge is to achieve recognition in real time, and to aid in visual analysis, a hardware architecture in FPGA (Field Programmable Gate Arrays) could be used for video processing focusing on the detection of moving objects using the background subtraction technique. And for that, some processes are critical as the digital image processing, video segmentation and real-time video processing. This paper´s proposal is the study of Digital Image Processing, Background Subtraction techniques and FPGA to develop an architecture for video processing to detect moving objects using the Background Subtraction technique. First it is discussed the basics of Digital Image Processing, Background Subtraction and FPGA, covering its main characteristics. Then it is explained the methodology applied in the development work. Is then described in detail the implementation process, and the end shows the final results and main conclusions for the project.