Digital reconstruction stage of parallel FBD sigma delta ADC implementation based on programmable digital oscillator in SDR receiver

This paper presents a programmable parallel frequency band decomposition (FBD) ADC which can be used in a software defined radio (SDR) receiver intended for wireless communication standards. The designed parallel ADC architecture is composed of 6 parallel branches based on discrete-time (DT) 4^th order ΣΔ modulators using single-bit quantizers. This paper is focused essentially on the digital reconstruction stage of the designed FBD architecture. The FBD architecture with a demodulation-based digital reconstruction is digitally implemented on a field programmable gate array (FPGA) target from Xilinx Inc. The frequency conversions performed in the digital reconstruction stage are ensured by a digital oscillator which is carefully tuned to obtain the required frequencies and phases for demodulation and modulation operations. Technical choices and simulation results are discussed. For UMTS use case, the implemented FBD ADC architecture ensures a computed signal-to-noise-ratio (SNR) equal to 74.42 dB.