Hierarchical performance modeling of embedded systems

The ability to estimate performance metrics such as latency (delay) at an early stage of final implementation in any embedded system is essential for efficient design specially realtime systems. Constructing performance models and evaluation techniques of a given system requires a significant effort. This paper presents a mapping scheme between a Functional Modeling Approach such as FSM, UML etc and an Analytical (Mathematical) Modeling Approach such as Hierarchical Performance Modeling (HPM) as a technique to find the expected average delay time for different layers of abstractions. A generic FSM is proposed to be used in order to estimate the expected average delay and to find a bottleneck of a system. A case study is presented to illustrate the concepts of the mapping scheme to estimate the delay and to determine the bottleneck(s).