Design of digital standard cell based on silicon tunnel field-effect transistor

Tunnel FETs was selected as the carrier of digital standard cell design since its excellent characteristics in low power consumption. This experiment contains the principle and characteristic of the Tunnel FETs, and specific standard cell circuit design based on the given model. In this design, we completed several combinational logic cells and sequential logic cells, and did the simulation. From the result of the simulation, we find that TFET devices´ speed is slower than MOS device, but the power consumption can reduce to less than 10% of the same size MOS device. Also, by comparing with the MOS devices, we made the corresponding layout design and DRC rule changes, and as one of the results, the area of TFET device is at least 30% larger the MOS device.