Dynamically Reconfigurable FIR Filter Design Based on FPGA

The traditional FIR filters based on reconfiguration have disadvantages with difficult to control and low-level automation. In addition, the traditional FIR filters take long time to configure. To solve these problems, a real-time reconfigurable FIR filter is proposed which is based on the dynamic partial reconfiguration technology of EAPR and based on multiply-accumulate structure. Finding the common and distinguish part by analyze the transfer function of the FIR filters within 1-15 order. Then the FIR filters are divided into static region and reconfigurable region. The design is proposed for the FPGA implementation of the reconfigurable FIR filter, which supports up to 121.265MHz operating frequency and 360KB file size about reconfiguration time is 4.57ms, when implemented in the Xilinx Virtex-5 FPGA device.