DocumentCode
3746049
Title
"Venice: A cost-effective architecture for datacenter servers"
Author
Rui Hou
Author_Institution
Institute of Computing Technology, Chinese Academy of Sciences
fYear
2015
Firstpage
1
Lastpage
1
Abstract
Dr. Rui Hou is VP, Processor Design, of Suzhou PowerCore Technology. He received his Bachelor´s and Master´s degree in computer science from Harbin Institute of Technology in 1999 and 2003 respectively, and earned his Ph.D in computer science from the Institute of Computing Technology of the Chinese Academy of Sciences in 2007. His main research interests are in the areas of data center systems and high-performance CPUs. Dr. Hou is currently leading a team to develop a high performance server processor based on IBM´s Power technology. He has led the design and development of an ARMv8 based many-core processor with a brand-new SMT-4 core that his team designed from the scratch. He has built prototypes systems enabling efficient resource sharing and high throughput computing inside the data centers. Dr. Hou is also an associate professor at Institute of Computing Technology. Before joining ICT in 2011, he had been working at IBM China Research Lab for four years. He has published over 20 peer-reviewed papers in various international conferences and journals, and filed more than 50 patent applications.
Keywords
"Computers","Servers","Computer science","Computer architecture","Prototypes","Resource management","Throughput"
Publisher
ieee
Conference_Titel
System-on-Chip Conference (SOCC), 2015 28th IEEE International
Electronic_ISBN
2164-1706
Type
conf
DOI
10.1109/SOCC.2015.7406895
Filename
7406895
Link To Document