A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS

A power-efficiency and speed-enhancing technique for binary-search ADCs is presented. Asynchronous timing and reduced-count binary-search architecture is implemented to achieve a high-speed operation. The distributed track-and-hold circuit is applied to relax the ENOB degradation caused by the comparator kickback noise and dynamic offset. A prototype 5-b 1-GS/s ADC was simulated in a 90nm CMOS technology. It consumes 2.7 mW from a 1.2 V supply. The ADC core occupies an active area of 0.012 mm2. With the post-layout simulation results, the SNDR and SFDR are 30 dB and 40 dB respectively. The equivalent ENOB is 4.55 b at the Nyquist-rate input. Its FoM is 115 fJ/conversion-step.