All-digital deskew buffer using a hybrid control scheme

This paper presents a deskew buffer using a hybrid control scheme to reduce the locking time. The function of duty cycle correction is provided as well to meet the common requirement of the digital system clock. With the aid of time-to-digital converter and successive approximation register schemes, the proposed circuit can speed up the locking process. It is designed and implemented in TSMC 0.18-μm CMOS process to validate its feasibility with low power consumption. The core circuitry occupies an area of 0.13 mm². The simulated results shows that the input clock rate is within 115~385 MHz with the duty cycle range of 15~85%. It can also perform the deskewing function in a closed-loop manner against the PVT variation.