DocumentCode
3746071
Title
A high-gain low-power low-noise-figure differential CMOS LNA with 33% current-reused negative-conductance accommodation structure
Author
To-Po Wang;Shih-Hua Chiang
Author_Institution
Department of Electronic Engineering, National Taipei University of Technology, Taipei 10608, Taiwan, R.O.C.
fYear
2015
Firstpage
78
Lastpage
81
Abstract
An integrated differential CMOS low-noise amplifier (LNA) with high gain, low dc power consumption, and low noise figure is presented in this paper. By introducing a current-reused negative-conductance accommodation structure to a differential LNA, the transconductance of the LNA can be effectively increased, leading to a performance enhanced differential LNA. To characterize the performance improvement of the differential LNA, two differential LNAs with and without the 33.3% current-reused negative-conductance accommodation structure were designed and fabricated for comparison. At supply voltages of 0.65-V VDD1 and 1.2-V VDD2, the measured gain of the differential LNA can be significantly improved from 13.1 dB to 15.8 dB, leading to a remarkable 2.7-dB gain increment. The measured dc power dissipation of the presented differential LNA with negative-conductance accommodation structure is 11.48 mW. In addition, the measured noise figure of the differential LNA with a current-reused negative-conductance accommodation structure is 3.3 dB. Compared to previously published 0.18-μm CMOS LNAs at the same frequency of interest, the proposed differential LNA with the current-reused negative-conductance accommodation structure achieves the high gain, low dc power dissipation, and low noise figure.
Keywords
"CMOS integrated circuits","Gain","Current measurement","Noise figure","Power demand","Voltage measurement"
Publisher
ieee
Conference_Titel
System-on-Chip Conference (SOCC), 2015 28th IEEE International
Electronic_ISBN
2164-1706
Type
conf
DOI
10.1109/SOCC.2015.7406917
Filename
7406917
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