Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems

Embedded memories are the key contributor to the chip area, dynamic power dissipation and also form a significant part of critical path for high performance advanced SoCs. Therefore, optimal selection of memory instances becomes imperative for SoC designers. While EDA tools have evolved over the past years to optimally select standard logic cells depending on the timing and the power constraints, optimal memory selection is largely a manual process. We propose a framework to optimize power, performance, and area (PPA) of a memory subsystem (MSS) by including floorplan dependent delays and power consumption in interconnects and glue logic of the MSS in the pre-RTL stage. Through this framework, we demonstrate that for a 4 Mb assembly of SRAM instances, dynamic power is reduced by 44%, area by 49%, and leakage by 71% with the floorplan aware selection. The framework has the capability to use different estimates, when routing congestion is important (for example, in low cost processes with less number of metal layers). We also show that the interconnect delays are reduced by about 68% and dynamic power by 58%, if additional metal layers are available for routing compared to a low cost 6 metal process.