Low-voltage 9T FinFETSRAM cell for low-power applications

In this paper, a novel multi-threshold 9T-SRAM cell using FinFET technology with improved read and write margins in comparison with the standard 6T-SRAM cell is proposed. By the use of this bit-cell at supply voltage of 200mV (800mV), read and write margins are improved by 92% (97%) and 2X (40%), respectively. The proposed design operates at supply voltages lower than 300mV that results in a 3X lower power consumption compared to the standard 6T-SRAM cell.