A digital background calibration technique for split DAC based SAR ADC by using redundant cycle

A digital background calibration technique for split CDAC mismatch is proposed. It uses the dummy capacitor to generate an extra calibration bit. The mismatch of the CDAC array is detected by the calibration bit and fed back to the compensation capacitor. A 9b 100MS/s SAR ADC is demonstrated in standard 65nm CMOS technology. Simulation results show that the DNL and INL can be decreased to ±0.1 LSB and +0.11/-0.13 LSB, respectively, after using this technique. The proposed calibration block consumes only 50μw from a 1.2V supply.