DocumentCode :
3748063
Title :
Moore´s law at 50: Are we planning for retirement?
Author :
Greg Yeric
Author_Institution :
ARM Research, Austin, TX, USA
fYear :
2015
Abstract :
The Moore´s Law era enjoyed a long run of lithographically-enabled pitch shrinking that directly reduced the cost per (von Neumann) function, as well as system power and performance improvements, via Dennard scaling. At the 50 year mark, the outlook for Moore´s Law is muddier, as we encounter exponential complexity in MOS VLSI scaling and an increasing set of design limitations, including power limits, parasitics, variability, and of course cost. To continue to create compelling product scaling, we will increasingly require "all-of-the-above" advancements, more directly linking the MOS VLSI scaling to the circuits to the systems, in an era where future systems may be different than the computers we are familiar with.
Keywords :
"Transistors","Logic gates","Random access memory","Metals","Very large scale integration","Optimization","Wires"
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
Type :
conf
DOI :
10.1109/IEDM.2015.7409607
Filename :
7409607
Link To Document :
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