Title :
A novel double-density, single-gate vertical channel (SGVC) 3D NAND Flash that is tolerant to deep vertical etching CD variation and possesses robust read-disturb immunity
Author :
Hang-Ting Lue;Tzu-Hsuan Hsu;Chen-Jun Wu;Wei-Chen Chen;Teng-Hao Yeh;Kuo-Pin Chang;Chih-Chang Hsieh;Pei-Ying Du;Yi-Hsuan Hsiao;Yu-Wei Jiang;Guan-Ru Lee;Roger Lo;Yan-Ru Su;Chiatze Huang;Sheng-Chih Lai;Li-Yang Liang;Chieh-Fang Chen;Min-Feng Hung;Chih-Wei Hu;C
Author_Institution :
Macronix International Co. Ltd, Emerging Central Lab. 16, Li-Hsin Road, Hsinchu Science Park, Hsinchu, Taiwan
Abstract :
We demonstrate a novel vertical channel 3D NAND Flash architecture - SGVC. SGVC device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. Our novel array decoding method enables a tight-pitch (25nm HP) metal BL design to fulfill the large page size (16KB for one plane) for high-performance NAND product. The SGVC flat cell possesses excellent P/E window of ~10V, small X/Y/Z adjacent-cell interferences, good self-boosting inhibit, and >10K P/E cycling endurance. Due to the advantage of flat cell that is insensitive to etching CD, SGVC device is tolerant to the non-ideal vertical etching and has shown excellent device uniformity from layer to layer. In sharp contract to GAA VC, SGVC suffers no penalty from field-enhancement effect, thus has shown very robust read-disturb immunity against long-term gate stressing. Due to (1) two physical bits per X-Y cell footprint, and (2) efficient array design with minimal overhead, SGVC architecture has 2 to 4 times memory density than GAA VC 3D NAND at the same stacking layer number.
Keywords :
"Computer architecture","Logic gates","Microprocessors","Three-dimensional displays","Etching","Programmable logic arrays","Flash memories"
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
DOI :
10.1109/IEDM.2015.7409617