Title :
A floating gate based 3D NAND technology with CMOS under array
Author :
Krishna Parat;Chuck Dennison
Author_Institution :
Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA 95054
Abstract :
NAND Flash has followed Moore´s law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue the scaling. This paper describes a floating gate based 3D NAND technology with superior cell characteristics relative to 2D NAND, and CMOS under array for high Gb/mm2 density.
Keywords :
"Three-dimensional displays","Logic gates","Computer architecture","Microprocessors","Nonvolatile memory","CMOS integrated circuits","Flash memories"
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
DOI :
10.1109/IEDM.2015.7409618
