Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices

A CSE (charge storage efficiency) model is proposed to explain the origin of ISPP slope degradation for various charge-trapping NAND Flash devices. Experimentally it is often observed that the programming window is generally degraded as device dimension scales [1], suggesting a strong size effect. Through our model analysis, it is clarified that for a given amount of trapped electron density in the nitride, the programmed Vt shift is gradually reduced with scaled device dimension owing to the increased fringe field effect. The fringe-field effect can be viewed as the increase of effective top-oxide capacitance, leading to the reduced weighting factor of charge storage. We therefore define a CSE value (<;1) to quantitatively account for the fringe field effect that retards the FN programming. Our model suggests that the ISPP slope is equal to CSE. Furthermore, CSE also impacts the stored electron number, retention, and interference. Optimization methods to improve CSE are studied.