• DocumentCode
    3748095
  • Title

    Implantation free GAA double spacer poly-Si nanowires channel junctionless FETs with sub-1V gate operation and near ideal subthreshold swing

  • Author

    Po-Yi Kuo;Jer-Yi Lin;Tien-Sheng Chao

  • Author_Institution
    Department of Electrophysics, National Chiao Tung University, Hsinchu 300, Taiwan
  • fYear
    2015
  • Abstract
    The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (DNW) - length (LNW) × width (WNW) × thickness (TNW) - to 80nm×13nm×3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) ~ 61 mV/dec., steep driving swing (D.S.) ~ 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.
  • Keywords
    "Logic gates","Field effect transistors","Doping","Voltage measurement","Nanowires","Grain boundaries","Electric variables"
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2015 IEEE International
  • Electronic_ISBN
    2156-017X
  • Type

    conf

  • DOI
    10.1109/IEDM.2015.7409639
  • Filename
    7409639
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3748095