Title :
2RW dual-port SRAM design challenges in advanced technology nodes
Author :
Koji Nii;Makoto Yabuuchi;Yoshisato Yokoyama;Yuichiro Ishii;Takeshi Okagaki;Masao Morimoto;Yasumasa Tsukamoto;Koji Tanaka;Miki Tanaka;Shinji Tanaka
Author_Institution :
Renesas Electronics Corporation, Tokyo, 187-8588, Japan
Abstract :
We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.
Keywords :
"Random access memory","FinFETs","Layout","CMOS integrated circuits","Current measurement","CMOS technology","Couplings"
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
DOI :
10.1109/IEDM.2015.7409673
