Assessing the impact of RTN on logic timing margin using a 32nm dual ring oscillator array

This paper presents a novel method for characterizing the impact of random telegraph noise (RTN) on logic timing margin under sub-0.5V supply voltages. The proposed dual ring oscillator array test structure improves the frequency measurement resolutions of the tested-and-proven beat frequency detection (BFD) technique by pairing a ROSC from one array with a ROSC from a second array having a similar frequency. Detailed circuit level RTN data was collected from a 32nm HKMG test chip, including voltage stress results. Measured data confirms that the proposed dual-array technique is effective in collecting high quality RTN statistics at sub-0.5V. The impact of RTN on logic timing margin is estimated based on the measured frequency data.