DocumentCode
3748208
Title
Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass
Author
Y. Sasaki;R. Ritzenthaler;Y. Kimura;D. De Roest;X. Shi;A. De Keersgieter;M. S. Kim;S. A. Chew;S. Kubicek;T. Schram;Y. Kikuchi;S. Demuynck;A. Veloso;W. Vandervorst;N. Horiguchi;D. Mocuta;A. Mocuta;A. V-Y. Thean
Author_Institution
imec, Kapeldreef 75, B-3001 Leuven, Belgium
fYear
2015
Abstract
We demonstrate a NMOS Si Bulk-FinFET with extension doped by Phosphorus doped Silicate Glass (PSG). Highly doped PSG (6e21 cm-3) was used as a diffusion source. SiO2 cap on PSG decreased sheet resistance (Rs) due to less out diffusion of P. Even when thin SiO2 exists at the interface between Si and PSG, P diffused from PSG into Si. Thanks to the high etch rate of the PSG/SiO2 cap stack after drive-in anneal, the PSG/SiO2 cap was successfully removed by HF with minimum removal of STI and gate hard mask oxide. PSG provides damage free and uniform sidewall doping to fin. On current ION is improved by 20% for LG in the 30-24 nm range, with similar IOFF and better DIBL compared to P ion implanted reference.
Keywords
"Silicon","Annealing","FinFETs","Doping","Hafnium","Logic gates","Implants"
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN
2156-017X
Type
conf
DOI
10.1109/IEDM.2015.7409754
Filename
7409754
Link To Document