Tunneling field effect transistors: Device and circuit considerations for energy efficient logic opportunities

Any significant improvement in the energy efficiency of logic will require significantly lower supply voltages (VDD) while keeping leakage current low. The Tunneling Field-Effect Transistor (TFET) is a leading future transistor option because its potential for steep subthreshold swing (SS) enables more efficient low VDD operation. In contrast to the MOSFET, the TFET is not fundamentally limited to 60 mV/dec SS, so for a range of operating voltages TFET circuits can have lower leakage or higher performance [1]. The physics of TFET operation is different than the MOSFET (Fig. 1a) because it uses electric field control of the quantum tunneling effect through a barrier [2] for the transport. Steep SS is possible by filtering of high-energy carriers in the Fermi-tail of the conduction (or valence) band of the N-TFET (or P-TFET) [3]. The TFET physical structure can be like the MOSFET (e.g. planar, fin, nanowire), but requires opposite type doping in source and drain (Fig. 1a). With this structure, an asymmetric ID-VDS exists with low conduction at negative V_DS (or V_SD) for an N-TFET (or P-TFET) (Fig. 2) [4].