Quantifying the impact of gate efficiency on switching steepness of quantum-well tunnel-FETs: Experiments, modeling, and design guidelines

DC and RF characterization up to 10 GHz from RT to T = 77 K combined with detailed modeling are used for the first time in a comprehensive investigation of the impact of gate efficiency on the subthreshold swing (SS) in Quantum-well Tunnel-FETs (QWTFETs). Calibrated modeling of experimental InGaAs/GaAsSb QWTFETs based on IV, CV and RF measurements and full quantum-mechanical (QM) simulations suggest that only 55% of the gate voltage contributes to the tunneling current modulation which results in degraded switching steepness. This is due to the coupling of the tunneling junction with the MOS structure, that severely degrades the gate efficiency. The proposed model can be adapted to analyze the gate efficiency in various TFET designs, and/or to use in circuit simulation. Based on the QM simulations, design guidelines resulting in up to 1.4X improved gate efficiency to ~78% in our device structure are proposed.