Title :
Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200?S/?m at 50nm Lg using a replacement Fin RMG flow
Author :
N. Waldron;S. Sioncke;J. Franco;L. Nyns;A. Vais;X. Zhou;H. C. Lin;G. Boccardi;J. W. Maes;Q. Xie;M. Givens;F. Tang;X. Jiang;E. Chiu;A. Opdebeeck;C. Merckling;F. Sebaai;D. van Dorp;L. Teugels;A. Sibaja Hernandez;K. De Meyer;K. Barla;N. Collaert;Y-V. Thean
Author_Institution :
imec, Leuven, Belgium
Abstract :
We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.
Keywords :
"Logic gates","Very large scale integration","Indium gallium arsenide","Performance evaluation","Annealing","Whales","III-V semiconductor materials"
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
DOI :
10.1109/IEDM.2015.7409805
