DocumentCode :
3748266
Title :
Enhancement-mode single-layer CVD MoS2 FET technology for digital electronics
Author :
L. Yu;D. El-Damak;S. Ha;X. Ling;Y. Lin;A. Zubair;Y. Zhang;Y.-H. Lee;J. Kong;A. Chandrakasan;T. Palacios
Author_Institution :
Massachusetts Institute of Technology, Cambridge, MA, USA
fYear :
2015
Abstract :
2D nanoelectronics based on single-layer (SL) MoS2 offers great advantages for ubiquitous electronics. With new device technology, highly uniform E-mode FETs using SL CVD MoS2 with positive VT, large mobility, excellent subthreshold swing are achieved. The integrated inverter shows excellent voltage transfer characteristic, close to rail-to-rail operation, high noise margin, large voltage gain (~45) and small static power. The combinational and sequential digital circuits shown here serve as a toolbox of building blocks for realizing wide range of digital circuitry.
Keywords :
"Logic gates","Inverters","Field effect transistors","Latches","Dielectrics","Fabrication"
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
Type :
conf
DOI :
10.1109/IEDM.2015.7409814
Filename :
7409814
Link To Document :
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