Hardware/software implementation of an on-line machine learning algorithm

Online learning is a machine learning paradigm that is useful when data is not available all at once. In this paper we focus in real time applications for which data is being collected as the algorithm executes. The forgetron Algorithm [1] is an online learning algorithm that works under a limited memory constraint while guaranteeing a bound on the number of total mistakes. We have proposed a specific architecture for the forgetron algorithm using hardware/software based design in order to improve computation time in the training process. Experiments on real world data show the advantages of this implementation compared to an exclusive software implementation using a Xilinx Virtex II Pro FPGA with an embedded Power PC. These experiments validate the performance of the proposed architecture.