• DocumentCode
    3748293
  • Title

    Design of a 12.5 GS/s 5-bit folding A/D converter

  • Author

    Antonio Surano;Franco Maloberti

  • Author_Institution
    Department of Electronics, University of Pavia, Via Ferrata, 1 - 27100 - ITALY
  • fYear
    2010
  • Firstpage
    21
  • Lastpage
    24
  • Abstract
    A 12.5 GS/s 5-bit A/D converter is described. The architecture is a hybrid scheme with flash, single and double folding, able to obtain the optimum trade off between speed and power consumption. Simulations at the transistor level validate the proposed architecture.
  • Keywords
    "Analog-digital conversion","Calibration","Computer architecture","Power demand","Transistors","Signal resolution","Quantization (signal)"
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (LASCAS), 2010 First IEEE Latin American Symposium on
  • Type

    conf

  • DOI
    10.1109/LASCAS.2010.7410130
  • Filename
    7410130
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3748293