Piecewise linear-based hybrid simulation of MOS and Single-Electron circuits

CMOS downscaling and recent advances in Single-Electron devices - such as Single-Electron Transistors (SET), foreseen the combination of both devices in hybrid systems. Despite the current problems in manufacturing single-electron structures, there is an increasing need for improving the design-path of these systems by tackling several aspects, among them, device modelling for hybrid simulation. This paper introduces a model for the SET that can be easily combined with MOS models for co-simulation of hybrid systems. The model constitutes a functional model for the SET in the form of an explicit piecewise linear (PWL) formulation that has been coded in a high level language which is used in the electrical simulation of several hybrid digital circuits.