Optimized large size signed multipliers and applications in FPGAs

Arithmetic computation decomposition is a powerful strategy used to solve large and complicated computing problems. In this paper, efficient design methodologies and systematic approaches for realizing large size signed multipliers are presented based on the use of small-size embedded blocks in FPGAs. To demonstrate the effectiveness of our approach, two large size operand computations are realized using our optimized large size multipliers. These functions are complex multiplication and matrix multiplication. The implementations targeted Xilinx´ and Altera´s FPGAs. Significant improvements of performance and area usage have been achieved for both applications compared to traditional techniques.