Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3D technology

This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS-3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system. Its architecture is that of a self-biased inverter with dynamic offset correction. At simulation level, the comparator can reach a resolution of 0.75mV in an area of approximately 220μm2 with a time response of less than 200ns and a static power dissipation of 1.125μW.