DocumentCode :
3749389
Title :
Circuit level paralleling of devices using two-way DC block for efficient power combining
Author :
Sumit Srivastava;S.R. Panchal;D.R. Gandhi;Praveen Bharadhwaj;Surinder Singh
Author_Institution :
Space Applications Centre (SAC) ISRO Ahmedabad, India
fYear :
2015
Firstpage :
56
Lastpage :
59
Abstract :
This paper presents a novel means for paralleling transistors at circuit level for combining power using a Microstrip coupled line based "two-way DC block". This approach offers several features in a single elegant structure, such as: power division, impedance matching between an arbitrary source and loads, inherent DC blocking capability and convenient post-production tuning where necessary. The implemented amplifier achieves the above mentioned functionalities with 17.5 dB of gain in 200 MHz bandwidth and 30dBm of output power at 50% output drain efficiency at Ku band.
Keywords :
"Power amplifiers","Power generation","Microstrip","Load modeling","Impedance matching","Impedance","Logic gates"
Publisher :
ieee
Conference_Titel :
MTT-S International Microwave and RF Conference (IMaRC), 2015 IEEE
Electronic_ISBN :
2377-9152
Type :
conf
DOI :
10.1109/IMaRC.2015.7411419
Filename :
7411419
Link To Document :
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