Title :
TSV via last etch integration challenges and etch optimization
Author :
Woon Leng Loh;Qin Ren;King Jien Chui
Author_Institution :
Institute of Microelectronics, A?STAR (Agency for Science, Technology and Research) 11, Science Park Road, Science Park II, Singapore, 117685
Abstract :
In this paper, we reported the TSV Via last from backside (BVL) etch integration challenges and Etch process optimization. We demonstrated the 10×40 um TSV via last (BVL) etch integration and discussed on various TSV profile. The fabrication of BVL was also reported including temporary bonding, wafer planarization, TSV liner deposition and Via bottom 1st and 2nd etch characterization.
Keywords :
"Silicon","Etching","Plasmas","Dielectrics","Bonding","Optimization"
Conference_Titel :
Electronics Packaging and Technology Conference (EPTC), 2015 IEEE 17th
DOI :
10.1109/EPTC.2015.7412270
